The present invention relates to integrated circuit design, and more specifically, to global trace routing. In the design of integrated circuits, the three dimensional layout of a circuit may involve positioning millions of individual elements and routing connections between those elements. Routing is often broken into three hierarchical stages: global routing, track routing, and detail routing. Global routing determines the approximate paths for a net of interconnections between elements (also referred to as “wires” or “wiring”) in the presence of localized congestion (e.g., due to wires, components, or boundaries of the integrated circuit). Track routing uses the layout produced by global routing and attempts to validly assign wiring to components on specific layers of the circuit (e.g., not passing wires through each other or other elements). Finally, detail routing uses the track routing and attempts to connect all of the terminals through exact and legal routing structures.